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| 3-Bit Programmable Delay Modules PLDM7 Series FAST/TTL Logic 7 Delay Steps -- 7 ns Inherent Delay Available in Surface Mount Electrical Specifications at 25OC Error ref. 3-Bit TTL Delay per to 000 Part Number Step (ns) (ns) PLDM7-1 1.0 .4 .50 PLDM7-1.2 1.2 .4 .60 PLDM7-1.25 1.25 .5 .70 PLDM7-1.3 1.3 .5 .70 PLDM7-1.5 1.5 .5 .70 PLDM7-1.8 1.8 .6 .80 PLDM7-1.9 1.9 .7 .80 PLDM7-2 2.0 .7 .80 PLDM7-2.5 2.5 .7 .90 PLDM7-2.6 2.6 .7 .90 PLDM7-3 3.0 .7 1.0 PLDM7-5 5.0 1.0 1.5 PLDM7-8 8.0 1.2 2.5 PLDM7-10 10.0 1.5 3.0 FAST/TTL 3-Bit Schematic Vcc 16 P1 11 P2 10 P3 9 3-Bit Programmable Delay Line Output Buffer 4 IN 5 OUT 7 E 8 GND Initial Delay (ns) 000 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 7 1.0 Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1) 000 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 001 1.0 1.2 1.25 1.3 1.5 1.8 1.9 2.0 2.5 2.6 3.0 5.0 8.0 10.0 010 2.0 2.4 2.5 2.6 3.0 3.6 3.8 4.0 5.0 5.2 6.0 10.0 16.0 20.0 011 3.0 3.6 3.75 3.9 4.5 5.4 5.7 6.0 7.5 7.8 9.0 15.0 24.0 30.0 100 4.0 4.8 5.0 5.2 6.0 7.2 7.6 8.0 10.0 10.4 12.0 20.0 32.0 40.0 101 5.0 6.0 6.25 6.5 7.5 9.0 9.5 10.0 12.5 13.0 15.0 25.0 40.0 50.0 110 6.0 7.2 7.5 7.8 9.0 10.8 11.4 12.0 15.0 15.6 18.0 30.0 48.0 60.0 111 7.0 8.4 8.75 9.1 10.5 12.6 13.3 14.0 17.5 18.2 21.0 35.0 56.0 70.0 CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000." For example, the setting "111" delay of PLDM7-10 is 70.0 3.0ns ref. to "000," and 77.0 4.0ns referenced to the input. _ ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high. INPUT FAN-IN: Input, pin 4, is loaded by the internal passive network and 8 gate inputs (74S type). The source driving Pin 4 should be FAST/TTL (74S/74F) type or equivalent, and should not be used to drive any load other than the delay line input. Dimensions in Inches (mm) .810 (20.57) MAX. .400 (10.16) MAX. TEST CONDITIONS -- FAST / TTL VCC Supply Voltage ................................................ 5.00VDC Input Pulse Voltage ................................................... 3.20V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements made at 25OC 2. Delay Times measured at 1.50V level of leading edge. 3. Rise Times measured from 0.75V to 2.40V. 4. 10pf probe and fixture load on output. .260 .300 (6.60) (7.62) TYP. MAX. .120 (3.05) MIN. .010 (0.25) TYP. .020 (0.51) TYP. .050 .100 (1.27) (2.54) TYP. TYP. .300 (7.62) OPERATING SPECIFICATIONS VCC Supply Voltage ................................... 5.00 0.25 VDC ICC Supply Current ......................... 60 mA typ., 80 mA max Logic "1" Input *: VIH ..................... 2.00 V min., 5.50 V max. IIH ............................... 50 A max. @ 2.70V Logic "0" Input *: VIL ....................................... 0.80 V max. IIL ............................................ -2.0 mA mA VOH Logic "1" Voltage Out .................................. 2.40 V min. VOL Logic "0" Voltage Out ............................... 0.50 V max. PWI Input Pulse Width ............................. 40% of Delay min. Operating Temperature Range ........................ -0O to +70OC Storage Temperature Range ...................... -65O to +150OC * Refer to "INPUT FAN-IN" note above. IIL/IIH specified for Programming pins 9, 10 & 11. 16-Pin SMD Pkg. Unused leads are NOT removed. To Specify SMD Package, Add "G" Suffix to P/N Examples: PLDM7-1.25G, PLDM7-2G 1.02 (25.9) MAX. .400 (10.16) .285 (7.24) MAX. .010 (0.25) TYP. .020 (0.51) TYP. .040 (1.02) TYP. .100 (2.54) TYP. .015 (0.38) .025 (0.64) .510 (12.95) .480 (12.19) 6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH www.rhombus-ind.com UKRPEXV LQGXVWULHV LQF )RU RWKHU YDOXHV &XVWRP 'HVLJQV FRQWDFW IDFWRU\ sales@rhombus-ind.com 25 TEL: (714) 898-0960 FAX: (714) 896-0971 PLDM7-G 2001-01 |
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